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DATA SHEET
O K I G a A s P R O D U C T S
10-Gbps GaAs Family High-Speed Optical Communications System
April 1999
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CONTENTS
10-GHz GaAs Family .........................................................................................................................1 KGL4201
10-GHz 8:1 Multiplexer ............................................................................................................................. 3
KGL4202
10-GHz 1:8 Demultiplexer ........................................................................................................................ 7
GHDD4411
EX-OR Circuit.......................................................................................................................................... 11
GHDD4414
Decision Circuit with Phase Detector ...................................................................................................... 15
Oki Semiconductor
10-GHz GaAs Family
High-Speed Optical Communications Systems INTRODUCTION
Oki's 10-GHz logic devices are manufactured using a 0.2-m, ion-implanted process, which is similar to Oki's familiar 0.5-m telecommunications process. However, the 0.2-m process uses a phase-shifting edge line (PEL) masking method for gate fabrication. Gold-based, three-level metal interconnections are used for high density and shorter wiring paths. Layers 1 and 2 are signal lines. Layer 3, which is formed by electroplating, is used for ground or power supply lines because of its lower resistance. An optional buried "p" channel structure is adopted for reducing short channel effects. The following table shows the digital GaAs logic processes of the 10-GHz GaAs family. GaAs Logic Processes
Basic FET Process MESFET MESFET Pseudomorphic-inverted HEMT Pseudomorphic BP--MESFET Basic Gate Circuit DCFL or SBFL DCFL or SBFL DCFL or SBFL Analog Photo Masking I-line printing PEL PEL Deep UV Gate Length (m) 0.5 < 0.2 0.2 0.2 fT (GHz) 30 60 > 60 > 60 Gate Delays (ps) 25 9 7 - Application < 2.4 Gbps standard cell >12-Gbps hand-routed logic > 20-Gbps low-density logic Analog amplifier
The key to operating reliably at 10 Gbps is logic circuitry that can easily manipulate data at over 13 Gbps. The higher frequency overhead is required to meet the different clock skews encountered when designing and routing 10-Gbps data management hardware. The logic is either direct-coupled FET logic (DCFL) or source-coupled FET logic (SCFL). The low-drive disadvantage of DCFL can be improved by using super-buffer FET logic (SBFL). The basic speed of SBFL is slower than DCFL, but SBFL is faster with higher fanouts and longer metal runs. A designer selects the best performing logic for each logic element application. SBFLs used for clock distribution, output buffers, etc. Typical gate delays of 9 ps and power of 2 mW per gate are achieved. Register logic elements like D-flip flops are assembled using memory cell flip flops (MCFF) as shown in Figure 1.The operation speed of a MCFF, which is about twice that of a conventional 6 NOR-gate circuit, operates at very low power. To simplify device interconnections, AC-coupled clock and data input lines are created using the circuit shown in Figure 2.
FEATURES
* 10-Gbps operation: highest speed available * ECL level logic swings: easy interface to other logic * Inputs internally terminated: reduces noise and phase jitter * 50- I/Os: easy to interconnect hardware
Oki Semiconductor
1
s 10-GHz GaAs Family s --------------------------------------------------------------------------
Data
Q
Data Master Clock Clock Master/Slave Flip-Flop Slave
Q
Data
Out
Clock
Clock Flip-Flop
Figure 1. Memory Cell Flip-Flops
Data or Clock In 50
Dummy Gate Reference
Figure 2. AC-Coupled, Self-Biased Logic Input Many 10-Gbps inputs are self-biased and 50- terminated, for capacitance coupling. The outputs are DCcoupled to drive 50- ground terminated lines.
DATA SHEETS
This document contains data sheets for the KGL4201, KGL4202, GHDD4411, and GHDD4414 10-Gbps GaAs High-Speed Optical Communication Systems. Data sheets for other communication devices may be obtained from the Oki Semiconductor WEB site, www.okisemi.com or from the local sales office.
2 Oki Semiconductor
KGL4201
10-GHz 8:1 Multiplexer GENERAL DESCRIPTION
Oki's KGL4201 is a 10-GHz 8:1 multiplexer designed to operate in 10-Gbps communication links. This circuit synchronously merges eight 1.25-Gbps data streams, clocked at low frequency rates into a single 10-Gbps stream, clocked at the higher frequency. In the KGL4201 multiplexer, the 10-GHz master clock is first divided by two, then by four. The lower frequency components are first multiplexed by four, then the two groups are merged into a single data stream using the master 10-Gbps clock. Complementary 1/8 synchronous clock outputs are made available from the KGL4201 for use in synchronizing lower frequency logic. All signal interfaces are 50- with direct DC coupling on the 1.25-Gbps data inputs and phase-locked 1.25-Gbps clock outputs. The 10-Gbps data output and 10-GHz clock input are AC-capacitively-coupled for ease of interfacing at microwave speeds and reducing ground noise induced phase jitter. All package clock and data pins are separated by either ground or supply voltage pins to control the I/O impedance, maintain signal isolation and reduce phase noise. The KGL4201 is shipped in a 40-pin ceramic flat-package with impedance-controlling ground plane and flush mounting bottom heat sink.
FEATURES
* AC-coupled 10 Gbps I/O: eliminates DC coupled phase jitter * 1/8 clock generated on chip: easy to synchronize downstream logic * 2 V, 2.4 W * Isolated I/O pins: minimize noise and impedance variation * Packaged in 40-pin ceramic flat-package with ground plane and heat sink.
Oki Semiconductor
3
s KGL4201 s -----------------------------------------------------------------------------------
PIN CONFIGURATION
14.84 SQ 13.01 SQ 10.67 SQ
40 1 31 30
0.7 0.05 0.9 .005 1.7 0.15
11.43 SQ
10 11
21
2 0.3
1.27
40
14.84 SQ 20 13.01 SQ 0.4 0.05 11.0 SQ
31 30
0.125 0.05
Pin Configuration
Pin 1 2 3 4 5 6 7 8 9 10 Name GND Q GND Q GND GND 1/8CK GND 1/8CK VB Pin 11 12 13 14 15 16 17 18 19 20
1
Pin Name GND VDD D0
10
Pin 21 22 23 24 25
20 21
Pin Name VDD GND GND CK GND GND RCK GND GND GND
0.9 .005 0.7 0.05
Pin 31 32 33 34 35 36 37 38 39 40
Pin Name GND VDD D7 GND D5 D3 GND D1 VB VDD
GND
11
D2 D4 1.27
260.4 0.05 27 28 29 30 1.7 0.15
GND D6 GND
2 0.3 GND
BLOCK DIAGRAM
D0 D2 D4 D6 D1 D3 D5 D7 1/8CK
4:1 MUX
2:1 MUX
Output Latch
Q Q
delay
1/8CK
1/4 Divider
1/2 Divider
delay
4:1 MUX
CK
4
Oki Semiconductor
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ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS
Rated Value Parameter Power supply voltage for internal logic Power supply voltage for output buffer Operating temperature range at package base VDD VB TS Symbol Min 1.9 1.9 0 Typ 2.0 2.0 - Max 2.1 2.1 70 Unit V V C
DC CHARACTERISTICS
VDD = 2V 0.1V, VB=2V 0.1V Ts = 0 to 70C Rated Value Parameter Power dissipation High-level 1/8 CK output voltage Low-level 1/8 CK output voltage Data output voltage swing Clock input voltage swing High-level data input voltage Low-level data input voltage P VOH VOL VOD VCK VIDH VIDL 50- load Capacitive coupling Symbol Test Condition Min. - 0.85 0 0.7 0.5 0.8 0 Typ. 2.4 Max. 3.0 1.3 0.3 1.2 0.9 1.3 0.3 Unit W V V VP-P VP-P V V
AC CHARACTERISTICS
VDD = 2V 0.1V, VB=2V 0.1V Ts = 0 to 70C Rated Value Parameter Minimum clock period Setup time (Data to 1/8 CK ) Hold time (1/8 CK to Data) CK-D[7:0] phase margin Rise time (Q, Q) Fall time (Q, Q) tC tPS tDH tM tR tF Input clock period is 100 ps Symbol Test Condition Min. - 450 -400 550 20 20 Typ. - 500 -350 650 30 30 40 40 Max. 100 550 -300 Unit ps ps ps ps ps ps
Oki Semiconductor
5
s KGL4201 s -----------------------------------------------------------------------------------
INTERFACE TIMING
CK D0 D1 D2 D3 D4 D5 D6 D7 Q Q 1/8 CK 1/8 CK A1 B1 C1 D1 E1 F1 G1 H1 A1 A1 B1 B1 C1 C1 D1 D1 A2 B2 C2 D2 E2 F2 G2 H2 E1 E1 F1 F1 G1 G1 H1 H1 A2 A2 B2 B2 C2 C2 D2 D2 A3 B3 C3 D3 E3 F3 G3 H3 E2 E2 F2 F2 G2 G2 H2 H2 A3 A3 A4 B4 C4 D4 E4 F4 G4 H4 B3 B3 C3 C3
6
Oki Semiconductor
KGL4202
10-GHz 1:8 Demultiplexer GENERAL DESCRIPTION
Oki's KGL4202 is a 10-GHz 1:8 demultiplexer designed to operate in 10-Gbps communication links. This circuit synchronously separates a single 10-Gbps data stream, clocked at up to 10 GHz, into eight lower frequency data streams, clocked at lower frequency rates. In the KGL4202 demultiplexer, the 10-GHz master clock is first divided by two, then by four. The 10-Gbps data stream is first divided into two synchronous serial paths, then these two data streams are separated into four each lower speed data streams and brought out to data latched outputs. Complementary 1/8 synchronous clock outputs are made available from the KGL4202 for use in synchronizing lower frequency logic. All signal interfaces are 50 with all inputs internally terminated in 50 . Direct DC coupling is used on the 10-Gbps data input, the 1.25-Gbps data outputs and phase-locked 1.25-Gbps clock outputs. The 10GHz clock input is AC-capacitively-coupled for ease of interfacing at microwave speeds and reducing ground noise induced phase jitter. The package 10-GHz clock and 10-Gbps data pins are separated by ground pins to control the I/O impedance, maintain signal isolation and reduce phase noise. The eight data outputs are distributed to opposite sides of the package to facilitate hardware layout and reduce noise. Over one third of the chip power is due to the ten 50- outputs. The KGL4202 is shipped in a 40-pin ceramic flat-package with impedance-controlling ground plane and flush-mounting bottom heat sink.
FEATURES
* AC-coupled 10 Gbps I/O: eliminates DC coupled phase jitter * 1/8 clock generated on chip: easy to synchronize downstream logic * Isolated I/O pins: minimizes noise and impedance variation * 2 V, 3.2 W * Packaged in 40-pin ceramic flat-package with ground plane and heat sink
Oki Semiconductor
7
s KGL4202 s -----------------------------------------------------------------------------------
PIN CONFIGURATION
14.84 SQ 13.01 SQ 10.67 SQ
40 1 31 30
0.7 0.05 0.9 .005 1.7 0.15
11.43 SQ
10 11 20
21
2 0.3
1.27
0.4 0.05
0.125 0.05
Pin Configuration
Pin 1 2 3 4 5 6 7 8 9 10 Name GND 1/8CK GND 1/8CK RD GND N.C. GND GND VB Pin 11 12 13 14 15 16 17 18 19 20 Pin Name GND VDD Q1 GND Q3 Q5 GND Q7 VB GND Pin 21 22 23 24 25 26 27 28 29 30 Pin Name VDD GND GND CKIN GND GND RCK GND GND VB Pin 31 32 33 34 35 36 37 38 39 40 Pin Name GND VDD Q6 GND Q4 Q2 GND Q0 VB VDD
BLOCK DIAGRAM
Q0 Q2 Q4 Q6 Q1 Q3 Q5 Q7 1/8CK 1/8CK 1/8CK
D
1:2 DEMUX
1:4 DEMUX
1:4 DEMUX delay
1/8CK
CK
1/2 Divider
1/4 Divider
8
Oki Semiconductor
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ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
Rated Value Parameter Supply voltage for internal logic Supply voltage for output buffer Clock input Data inputs Temperature at package base under bias Storage temperature VDD VB CK D TS TST Symbol Min. -0.3 -0.3 -0.3 -0.3 -45 -45 Max. 2.3 2.3 1.5 1.5 100 125 Unit V V V V C C
RECOMMENDED OPERATING CONDITIONS
Rated Value Parameter Power supply voltage for internal logic Power supply voltage for output buffer Operating temperature range at package base VDD VB TS Symbol Min. 1.9 1.9 0 Typ. 2.0 2.0 - Max. 2.1 2.1 70 Unit V V C
DC CHARACTERISTICS
VDD = 2 V 0.1 V, VB=2 V 0.1 V TS = 0 to 70C Rated Value Parameter Power dissipation High-level 1/8CK output voltage Low-level 1/8CK output voltage Data input voltage swing Clock input voltage swing P VOH VOL VID VICK 50- load 50- load Capacitive coupling Capacitive coupling 0.85 0 0.5 0.5 Symbol Test Condition Min. Typ. 3.2 Max. 4.0 1.3 0.3 0.9 0.9 Unit W V V VP-P VP-P
AC CHARACTERISTICS
VDD = 2V 0.1V, VB=2V 0.1V Ts = 0 to 70C Rated Value Parameter Minimum clock period Setup time (D to CK ) Hold time (CK to D) CK-D phase margin 1/8CK to valid data delay tC tDS tDH tM tC8Q Input clock period is 100 ps -55 70 50 -40 -45 80 65 -10 20 Symbol Test Condition Min. Typ. Max. 100 -35 90 Unit ps ps ps ps ps
Oki Semiconductor
9
s KGL4202 s -----------------------------------------------------------------------------------
INTERFACE TIMING
CK D Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 1/8 CK 1/8 CK A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 A1 B1 C1 D1 E1 F1 G1 H1 F2 G2 H2 A3 B3 C3 D3 E3 A2 B2 C2 D2 E2 F2 G2 H2 F3 G3 H3 A4 B4 C4 A3 B3 C3 D3 E3 F3 G3 H3 D4
TIMING
tC CK tM
tDS D
tDH
1/8 CK
1/8 CK tC8Q Q[7:0] Valid Valid
10
Oki Semiconductor
GHDD4411
EX-OR Circuit GENERAL DESCRIPTION
Oki's GHDD4411 is a 10-GHz exclusive-OR/NOR circuit designed to function in 10-Gbps high-speed communication serial bit streams. The EX-OR must operate from both rising and falling edges at an equivalent speed of 20-Gbps non-return-to-zero (NRZ) signal to extract a 10-Gbps clock from a 10-Gbps signal. Using closely matched Gilbert cell circuitry, this device operates at over 10 Gbps using DCFL and SBFL logic from inverted HEMT technology. Internal input 50- terminations and a self-referencing bias voltage allow capacitive coupling, simplifying interconnections. The GHDD4411 EX-OR circuit is high-speed in a 28-pin ceramic flat package with impedance-controlling ground plane and flush-mounting bottom heat sink.
FEATURES
* EX-OR and EX-NOR: outputs optimized for performance * 1.5 V, 0.6 W: lowest power with 50- interfaces * Packaged in 28-pin ceramic flat package with ground plane and heat sink
Oki Semiconductor
11
s GHDD4411 s ----------------------------------------------------------------------------------
PIN CONFIGURATION
6 0.1 16 0.1 12 9.6 8
28 20
2
2.1 0.1 0.5 0.5 0.5
1
19
12 0.1 9 8.6 7
5
15
6
14
2
1.27 10.16
0.3
0.125
Dimensions in mm
15
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Signal IN1BS N.C. IN1RF N.C. VB GND EXOR GND N.C. N.C. N.C. GND EXNOR GND Input 1 bias input No Connect
Function
Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VB
Signal
Function Power supply (buffer) No Connect Input 2 bias reference output No Connect Input 2 bias input Ground Data input 2 Ground Power supply (logic circuit) No Connect Power supply (logic circuit) Ground Data input 1 Ground
N.C. IN2RF N.C. IN2BS GND IN2 GND VD N.C. VD GND IN1 GND
Input 1 bias reference output No Connect Power supply (buffer) Ground EX-OR output Ground No Connect No Connect No Connect Ground EX-NOR output Ground
12
Oki Semiconductor
11
--------------------------------------------------------------------------------- s GHDD4411 s
BLOCK DIAGRAM
IN1RF
IN1 EXNOR IN1BS EXOR IN2 IN2BS IN2RF
Oki Semiconductor
13
s GHDD4411 s ----------------------------------------------------------------------------------
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Suuply voltage for internal logic Supply voltage for outpu buffer Clock input Data input Temperature at package base under bias Storage temperature VDD VB CK D TS TST Symbol Min -0.3 -0.3 -0.3 -0.3 -45 -45 Max 2.3 2.3 1.0 1.0 100 125 Unit V V V V C C
Recommended Operating Conditions
Parameter Suuply voltage for internal logic Supply voltage for output buffer Operating temperature range at package base VDD VB TS Symbol Min. 1.4 1.4 0 Typ. 1.5 1.5 Max. 1.6 1.6 70 Unit V V C
VDD = 1.5 V 0.1, VB = 1.5 V 0.1, TS = 0 to 70 C
Parameter Power dissipation Input bit rate Data input voltage amplitude Data output voltage amplitude Data output rise/fall time P B VID VOD Capacitive coupling 50- load, Capacitive coupling 0.2 0.7 20 Symbol Condition Min. Typ. 0.6 10 0.8 Max. Unit W Gb/s VP-P VP-P ps
OUTPUT WAVEFORM
I63A-7, DEC12,5-7, 25C, P
Horizontal - 20ps/Div, Vertical - 200 mV/div
14
Oki Semiconductor
GHDD4414
Decision Circuit with Phase Detectors GENERAL DESCRIPTION
Oki's GHDD4414 is a 10-GHz decision circuit designed to strip data from high-speed serial bit streams in 10-Gbps communication links. Using a clock input at up to 10 GHz and using D-flip-flops, EX-ORs, and phase detectors, this circuit separates a 10-Gbps data stream into: clock output, data output, "phase" variation output, and data density output. A 10-GHz master clock drives two D-flip-flops in this circuit. Buffered input data is clocked through the first flip-flop, then the second, "data out" is taken from the first flip-flop. The data input buffer is composed of a series of inverters to delay the signal and obtain a small decision ambiguity. A phase comparison is made of the buffered data and data from flip-flop one; a second phase comparison is made of the output of flip-flops one and two. The phase detectors are modified EX-OR circuits with resistor summing of the logic gates to permit analog measurement of their outputs. Any change in the timing relationships between the clock and data is seen at the output of the first phase detector. The second flip-flop operates as a 1-bit shift register with fixed 360-deg phase shift. The second phase detector output depends only upon the transition density (speed of rise and fall transitions) of the input data signal. All signal interfaces are 50- with all inputs internally terminated in 50 . The 10-GHz clock and data inputs are AC capacitively-coupled for ease of interfacing at microwave speeds and reducing ground noise induced phase jitter. Data and phase outputs are DC-coupled.
FEATURES
* Phase detectors on chip: verifies data integrity * Isolated 10-Gbps input pins: minimizes noise and impedance variation * 1.5 V, 1 W: lowest power with 50- interfaces * 28-pin ceramic flat package with impedance controlling ground plane and flush mount heat sink
Oki Semiconductor
15
s GHDD4414 s ----------------------------------------------------------------------------------
PIN CONFIGURATION
6 0.1 16 0.1 12 9.6 8
28 20
2
2.1 0.1 0.5 0.5 0.5
1
19
12 0.1 9 8.6 7
5
15
6
14
2
1.27 10.16
0.3
0.125
Dimensions in mm
15
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Signal CBS NC CMB NC VB GND DOUT GND NC NC NC GND COUT GND Clock output Data output Powr supply (buffer) Clock bias input
Function
Pin 15 16 VB P1 P2 P3 VD
Signal
Function Power supply (buffer) Phase detector output Phase detector ref. output 1 Phase detector ref. output 2 Power supply (logic circuit)
Clock output duty monitor
17 18 19 20 21 22 23 24 25 26 27 28
GND DIN GND DBS DRF VD GND CK GND Clock input Data bias input Data bias reference output Power supply (logic circuit) Data input
16
Oki Semiconductor
11
--------------------------------------------------------------------------------- s GHDD4414 s
BLOCK DIAGRAM
DOUT Phase Detector PD P1
PD
P2
D DBS DRF
D
Q
D
Q
PD
P3
LPF CK CBS
CMB COUT
APPLICATION BLOCK DIAGRAM
Fiber Input
Pin-PD & PreAmp
AGC Amp
Decision Circuit Clock
Out
Delay
Rectifier
Filter
Phase Shifter
Limiting Amp
Oki Semiconductor
17
s GHDD4414 s ----------------------------------------------------------------------------------
ELECTRICAL CHARACTERISTICS
VDD = 1.5 V 0.1 V, VB = 1.5 V 0.1 V, TS = 0 to 70C
Parameter Power dissipation Decision ambiguity Phase margin Data input voltage amplitude Clock input voltage amplitude Data output voltage amplitude Clock output voltage amplitude Clock output duty cycle Clock to data delay Phase detection sensitivity Symbol P VIDEC VID VIC VOD VOC DTYC CD V 10 Gbps PRBS: 215 -1 50 load capacitive coupling 10 Gbps PRBS: 215 -1 Capacitive coupling 0.4 0.7 0.7 40 25 0.28 60 45 Condition Min. Max. 1 0.05 250 0.8 0.8 Unit W VP-P degree VP-P VP-P VP-P VP-P % ps mV/degree
Phase Detection Characteristics (DIN Amplitude = 0.7-VP-P)
CIN Delay (ps) +29 0 -29 P1 (V) 0.350 0.383 0.424 P2 (V) 0.343 0.340 0.342 P3 (V) 0.443 0.443 0.443 Maximum delay for ER <10 Center of phase margin Minimum delay for ER <10-10 Comments
-10
PHASE DETECTOR CIRCUIT
Input 1
Output
Input 2
18
Oki Semiconductor
--------------------------------------------------------------------------------- s GHDD4414 s
PHASE DETECTION BETWEEN SIGNAL AND CLOCK AT 10 Gbps
400 P1[mV] P2[mV] P3[mV]
350 Output Voltage of PD (mV)
300
250
Error Free Range 200 -270 -180 -90 0 90 180 270
Phase Variation (degree)
TIMING
Data
Clock 200mV/div
25ps/div
Oki Semiconductor
19
s GHDD4414 s ----------------------------------------------------------------------------------
20
Oki Semiconductor
The information contained herein can change without notice owing to product and/or technical improvements. Please make sure before using the product that the information you are referring to is up-to-date. The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product. When you actually plan to use the product, please ensure that the outside conditions are reflected in the actual circuit and assembly designs. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in connection with the use of product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges, including but not limited to operating voltage, power dissipation, and operating temperature. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,office automation, communication equipment, measurement equipment, consumer electronics, etc.).These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans. Such applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, including life support and maintenance. Certain parts in this document may need governmental approval before they can be exported to certain countries. The purchaser assumes the responsibility of determining the legality of export of these parts and will take appropriate and necessary steps, at their own expense, for export to another country. Copyright 1999 Oki Semiconductor Oki Semiconductor reserves the right to make changes in specifications at anytime and without notice. This information furnished by Oki Semiconductor in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Oki Semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Oki.
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